The present invention generally relates to the configuration of programmable logic devices, and more particularly to defining connections between logic cores on programmable logic devices.
Field programmable gate arrays (FPGAs), first introduced by Xilinx in 1985, are becoming increasingly popular devices for use in electronics systems. For example, communications systems employ FPGAs in large measure for their re-programmability and high speed. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability.
The field of reconfigurable computing has advanced steadily for the past decade, using FPGAs as the basis for high-performance reconfigurable systems. Run-Time Reconfigurable (RTR) systems distinguish themselves by performing circuit logic and routing customization at run-time. RTR systems using FPGAs are expected to result in systems that require less hardware, less software, and fewer input/output resources than traditional FPGA-based systems. However, scarcity of software that supports RTR is believed to be one reason that RTR has been outpaced by research in other areas of reconfigurable computing.
Whereas the time taken to generate a programming bitstream is generally not real-time critical with traditional systems having FPGAs, the time required to generate the programming bitstream for an RTR system may be critical from the viewpoint of a user who is waiting for the FPGA to be reconfigured. Thus, in a runtime environment it is expected that the reconfiguration process will require no more than a few seconds, or even a fraction of a second.
In both static and run-time configuration environments, logic cores are utilized to quickly integrate previously implemented functionality into a workable system. Each logic core is comprised of logic that performs a specific function when implemented on an FPGA. In the JBits environment that is available from Xilinx, a library of logic cores can be defined and made available for use in run-time configuration. JBits provides Java classes for defining and implementing cores.
The relationships between cores are generally defined by the various interconnections, which are characterized herein as the pin connections. That is, a certain output pin of a first core is connected to a certain input pin of a second core. In the context of configurable logic blocks (CLBs) of an FPGA, a xe2x80x9cpinxe2x80x9d may correspond, for example, to the output of a CLB multiplexer or the input to a lookup table. Other programmable logic devices (PLDs) have comparable xe2x80x9cpinsxe2x80x9d.
Reconfiguration of an FPGA may include routing and rerouting connections between the logic sections. Present run-time routing methods provide a great deal of program control over the routing process. For example, the JBits environment allows a program to manipulate individual bits in the configuration bitstream for configuring routing resources. While this approach provides a great deal of flexibility, the drawback is added program complexity.
In some instances, multiple logic cores are assembled into a hierarchy of cores to implement a higher level function. Tracking the various pin connections between the cores can be burdensome and error-prone, thereby impeding the development of RTR systems. A method and apparatus that addresses the aforementioned problems, as well as other related problems, is therefore desirable.
In various embodiments, a method and apparatus are provided for generating a configuration bitstream for a programmable logic device using logic ports that are associated with logic cores. Logic ports are associated with respective ones of a plurality of logic cores, and logical connections are made between selected ones of the ports of the logic cores. Source pins, wherein a pin represents an output resource of a programmable element of the programmable logic device, are associated with selected ones of the ports. A sink pin represents an input resource of a programmable element of the programmable logic device, and sink pins are associated with selected ones of the ports. By providing a level of abstraction for defining inputs to and outputs from logic cores that is above the level of physical input/output resources, run-time parameterizable logic cores can be interconnected by reference to logic input and output relationships between cores rather than by reference to pin-to-pin connections between cores. In response to a route programming interface call that references a source port and a sink port, bits for the configuration bitstream are generated for routing resources to connect selected ones of the source pins to selected ones of the sink pins.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims that follow.